Click here to return to the VHDL Reference Guide. (last edit: 24. september 2012)

Wait

A sequential statement which waits for an event on a signal in the sensitivity list, for a Condition to become true, or for a timeout.

Syntax

  [Label:] wait [on SensitivityList] [until Condition]
                [for TimeExpression];

  SensitivityList = SignalName, ...
    

Where

See Sequential Statement

Rules

When an event occurs on a signal in the sensitivity list, the Condition is checked. If True, the process resumes. In any case, the process resumes after the TimeExpression has elapsed. If the on part is omitted, a sensitivity list is built from the signals within the Condition.

Things to remember

Wait until is edge triggered; the Condition is only tested when an event occurs on a signal in the wait statement. Thus, wait until Now = 1 US; would wait forever!

Synthesis

Wait for, wait on and wait; are not synthesizable. Wait until is synthesizable only when used to synchronize a process to a clock edge, e.g. wait until Clock = '1'; (see Process).

Tips

The wait for and wait; statements are particularly useful for defining test vectors, as shown in the example below. The wait; at the end of the process is necessary to stop the process looping.

Example

  (See Process)
  -- Generating Test Vectors:
  constant Period: TIME := 25 NS;
  ...
  Stimulus: process
  begin
    A <= "0000";
    B <= "0000";
    wait for Period;
    A <= "1111";
    wait for Period;
    B <= "1111";
    wait for Period;
    wait;
  end process;
    

See Also

Process